Active Low SR Latch Or Flip Flop: What Is It? (Plus Truth Table)

Contents

• What is an Active Low SR Latch?
• Active Low SR Latch Truth Table

• Active Low SR Latch Definition: An active low SR latch is a digital storage device that changes its output state based on low (0) input signals.
• SET Condition: The latch sets, or Q becomes 1, when S is 0 and R is 1, demonstrating how input affects output.
• RESET Condition: It resets, meaning Q becomes 0, when R is 0 and S is 1, further showing input-output dynamics.
• Truth Table Clarification: The truth table for the active low sr latch clearly lists all possible input combinations and their effects on the outputs.
• Unpredictable State Warning: It’s crucial to avoid the condition where both S and R are 0 as it leads to unpredictable outputs, highlighting the need for careful input planning.

What is an Active Low SR Latch?

An active low SR latch (or active low SR Flip Flop) is a type of latch which is SET when S = 0(LOW). An active low SR latch is typically designed by using NAND gates. The logical circuit for a SR latch is shown below.

In the above logic circuit if S = 0 and R = 1, Q becomes 1. Let us explain how.

• NAND gate always gives output 1 when at least one of the inputs is 0.
• So, when S is applied as 0 the output of gate G1 i.e. Q is 1 irrespective of the condition of second input to the gate.
• Now, Q is input of gate G2 so both the inputs of G2 become 1 as R is already 1. So output of G2 is now or 0.
• So whatever may be the previous condition of Q, it always becomes Q = 1 and = 0 when S = 0 and R = 1. This is called SET condition of the latch.

In the above logic circuit if S = 1 and R = 0, Q becomes 0. Let us explain how.

• As we already said, a NAND gate always gives output 1 when at least one of the inputs is 0.
• So when R is applied as 0, the output of gate G2 i.e. is 1 irrespective of the condition of second input Q to the gate.
• So whatever may be the previous condition of , it always becomes 1 this 1 is then fed back to input of gate G1. As here S is already 1, both inputs of G1 are 1. Hence output of G1 i.e. Q will be 0. So Q = 0 and = 1 when, S = 1 and R = 0. This is called RESET condition of the latch.

In the circuit, if both S and R are 1, Q maintains its previous state. Here’s how it works.

• First suppose Q is previously 1.
• Now both inputs of G2 are 1 as R = 1 and Q = 1. So output of G2 i.e. is or 0.
• Now the inputs of G1 are 1 and 0 as R = 1 and = 0. So output of G1 i.e. Q is or 1.
• Now suppose Q is previously 0.
• Now the inputs of G2 are 1 and 0 as R = 1 and Q = 0. So output of G2 i.e. is or 1.
• Now both inputs of G1 are 1 as S = 1 and = 1. So output of G1 i.e. Q is or 0.
• So it is proved that Q remains same as it is when, S = 1 and also R = 1.

In the above logic circuit if S = 0 and also R = 0, the condition of Q is totally unpredictable. Let us explain how.

• First suppose Q is previously 0.
• Now both inputs of G2 are 0 as R = 0 and Q = 0. So output of G2 i.e. is or 1.
• Now the inputs of G1 are 0 and 1 as S=0 and = 1. So output of G1 i.e. Q is or 1. That means Q is changed.
• Now Q is 1. So inputs of G2 are 0 and 1 as R = 0 and Q = 1. So output of G2 i.e. is or 1. That means is unchanged.
• Now the inputs of G1 are 0 and 1 as S=0 and = 1. So output of G1 i.e. Q is or 1. That means Q is unchanged.

When both S and R are 0, the output Q’s behavior becomes unpredictable, making this a typically avoided condition in SR latches.

Active Low SR Latch Truth Table

The truth table for an active low SR flip flop (i.e. SR Latch) has been shown in the table below.

There are also D Latches, JK Flip Flops, and Gated SR Latches. You can learn more about active low SR flip flops and other logic gates by checking out our full list of logic gates questions.