Verilog Timescale - ChipVerify
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- Syntax
- Example #1: 1ns/1ns
- Example #2: 10ns/1ns
- Example #3: 1ns/1ps
Verilog simulation depends on how time is defined because the simulator needs to know what a #1 means in terms of time. The `timescale compiler directive specifies the time unit and precision for the modules that follow it.
Syntax
`timescale <time_unit>/<time_precision> // Example `timescale 1ns/1ps `timescale 10us/100ns `timescale 10ns/1nsThe time_unit is the measurement of delays and simulation time while the time_precision specifies how delay values are rounded before being used in simulation.
Use the following timescale constructs to use different time units in the same design. Remember that delay specifications in the design are not synthesizable and cannot be converted to hardware logic.
- `timescale for base unit of measurement and precision of time
- $printtimescale system task to display time unit and precision
- $time and $realtime system functions return the current time and the default reporting format can be changed with another system task $timeformat.
| Character | Unit |
|---|---|
| s | seconds |
| ms | milliseconds |
| us | microseconds |
| ns | nanoseconds |
| ps | picoseconds |
| fs | femtoseconds |
The integers in these specifications can be either 1, 10 or 100 and the character string that specifies the unit can take any value mentioned in the table above.
Example #1: 1ns/1ns
// Declare the timescale where time_unit is 1ns // and time_precision is also 1ns `timescale 1ns/1ns module tb; // To understand the effect of timescale, let us // drive a signal with some values after some delay reg val; initial begin // Initialize the signal to 0 at time 0 units valTag » How To Enable And Disable Calculator Mode In Verilog
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