5 Nm Process - Wikipedia

Semiconductor manufacturing processes

Semiconductordevicefabrication
MOSFET scaling(process nodes)
020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977  1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2025
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
v t e

In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the "5 nm" process as the MOSFET technology node following the "7 nm" node. In 2020, Samsung and TSMC entered volume production of "5 nm" chips, manufactured for companies including Apple, Huawei, Mediatek, Qualcomm and Marvell.[1][2]

The term "5 nm" does not indicate that any physical feature (such as gate length, metal pitch or gate pitch) of the transistors is five nanometers in size. Historically, the number used in the name of a technology node represented the gate length, but it started deviating from the actual length to smaller numbers (by Intel) around 2011.[3] According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, the 5 nm node is expected to have a gate length of 18nm, a contacted gate pitch of 51nm, and a tightest metal pitch of 30nm.[4] In real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.[5][6]

History

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Background

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Quantum tunnelling effects through the gate oxide layer on "7 nm" and "5 nm" transistors became increasingly difficult to manage using existing semiconductor processes.[7] Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[8][9]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[10][11]

In 2015, IMEC and Cadence fabricated 5 nm test chips. The fabricated test chips were not fully functional devices, but rather are to evaluate patterning of interconnect layers.[12][13]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the "5 nm" node.[14]

In 2017, IBM revealed that it had created "5 nm" silicon chips,[15] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2, for a total of 30 billion transistors (1667 nm2 per transistor or 41 nm actual transistor spacing).[16][17]

Commercialization

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In April 2019, Samsung Electronics announced they had been offering their "5 nm" process (5LPE) tools to their customers since 2018 Q4.[18] In April 2019, TSMC announced that their "5 nm" process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.[19] For the expected 28 nm minimum metal pitch, SALELE is the proposed best patterning method.[20]

For their "5 nm" process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.[21]

In October 2019, TSMC reportedly started sampling 5 nm A14 processors for Apple.[22] At the 2020 IEEE IEDM conference, TSMC reported their 5 nm process had 1.84x higher density than their 7nm process.[23] At IEDM 2019, TSMC revealed two versions of 5 nm, a DUV version with a 5.5-track cell, and an (official) EUV version with a 6-track cell.[24][25]

In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their "5 nm" test chips with a die size of 17.92 mm2.[26] In mid 2020 TSMC claimed its (N5) "5 nm" process offered 1.8x the density of its "7 nm" N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.[27]

On 13 October 2020, Apple announced a new iPhone 12 lineup using the A14. Together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, the A14 and Kirin 9000 were the first devices to be commercialized on TSMC's "5 nm" node. Later, on 10 November 2020, Apple also revealed three new Mac models using the Apple M1, another 5 nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm2.[28]

In October 2021, TSMC introduced a new member of its "5 nm" process family: N4P. Compared to N5, the node offered 11% higher performance (6% higher vs N4), 22% higher power efficiency, 6% higher transistor density and lower mask count. TSMC expected first tapeouts by the second half of 2022.[29][30][needs update]

In December 2021, TSMC announced a new member of its "5 nm" process family designed for HPC applications: N4X. The process featured optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors. The process was expected at that time to[needs update] offer up to 15% higher performance vs N5 (or up to 4% vs N4P) at 1.2 V and supply voltage in excess of 1.2 V. TSMC, at that time, said that they expected[needs update] N4X to enter risk production by the first half of 2023.[31][32][33]

In June 2022, Intel presented some details about the Intel 4 process (known as "7 nm" before renaming in 2021): the company's first process to use EUV, 2x higher transistor density compared to Intel 7 (known as "10 nm" ESF (Enhanced Super Fin) before the renaming), use of cobalt-clad copper for the finest five layers of interconnect, 21.5% higher performance at iso power or 40% lower power at iso frequency at 0.65 V compared to Intel 7 etc. Intel's first product to be fabbed on Intel 4 was Meteor Lake, powered on in Q2 2022 and scheduled for shipping in 2023.[34] Intel 4 has contacted gate pitch of 50 nm, both fin and minimum metal pitch of 30 nm, and library height of 240 nm. Metal-insulator-metal capacitance was increased to 376 fF/μm², roughly 2x compared to Intel 7.[35] The process was optimized for HPC applications and supported voltage from <0.65 V to >1.3 V. WikiChip's transistor density estimate for Intel 4 was 123.4 Mtr./mm², 2.04x from 60.5 Mtr./mm² for Intel 7. However, high-density SRAM cell had scaled only by 0.77x (from 0.0312 to 0.024 μm²) and high-performance cell by 0.68x (from 0.0441 to 0.03 μm²) compared to Intel 7.[36][needs update]

On 27 September 2022, AMD officially launched their Ryzen 7000 series of central processing units, based on the TSMC N5 process and Zen 4 microarchitecture.[37] Zen 4 marked the first utilization of the 5 nm process for x86-based desktop processors. In December 2022 AMD also launched the Radeon RX 7000 series of graphics processing units based on RDNA 3, which also used the TSMC N5 process.[38]

Nodes

[edit] 5 nm

IRDS roadmap 2017[39]		Samsung[40][41][42][43][44]		TSMC[40]
Process name	7 nm	5 nm	5LPE	5LPP	N5	N5P	4N[45]
Transistor density (MTr/mm2)	Un­known	Un­known	126.9[44]	Un­known	138.2[46][47]		Unknown
SRAM bit-cell size (μm2)	0.027[48]	0.020[48]	0.0262[49]		0.021[49]		Unknown
Transistor gate pitch (nm)	48	42	57		51		Unknown
Interconnect pitch (nm)	28	24	36	Un­known	28[50]		Unknown
Release status	2019	2021	2018 risk production[18]2020 production	2022 production	2019 risk production[19]2020 production	2020 risk production2021 production	2022 production

4 nm process nodes

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Samsung[40][42][43][44][51]					TSMC				Intel[52][34]
Process name	4LPESF4E	4LPPSF4	4LPP+SF4P	4HPCSF4X	4LPASF4U	N4	N4P	N4X[31][32][33]	N4C[53]	4[54][55]
Transistor density (MTr/mm2)	137[44]		Un­known	Un­known	Un­known	143.7[56]		Un­known	Un­known	123.4[36]
SRAM bit-cell size (μm2)	0.0262[49]		Un­known	Un­known	Un­known	Un­known		Un­known	Un­known	0.024[49]
Transistor gate pitch (nm)	57		Un­known	Un­known	Un­known	51		Un­known	Un­known	50
Interconnect pitch (nm)	32		Un­known	Un­known	Un­known	28		Un­known	Un­known	30
Release status	2020 risk production2021 production	2022 production	2023 production	2024 production	2025 production	2021 risk production2022 production	2022 risk production2022 production	Risk production by H1 20232024 production	2025 production	2022 risk production[57]2023 production[58]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[59][60]

Beyond 4 nm

[edit] Main article: 3 nm process

"3 nm" is the usual term for the next node after "5 nm". As of 2023[update], TSMC has started producing chips for select customers, while Samsung and Intel have plans for 2024.[52][61][62][63]

"3.5 nm" has also been given as a name for the first node beyond "5 nm".[64]

References

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1. ^ Cutress, Dr Ian. "'Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5". AnandTech. Archived from the original on 30 August 2020. Retrieved 28 August 2020.
2. ^ "Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology". HPCwire. Archived from the original on 15 September 2020. Retrieved 28 August 2020.
3. ^ "No More Nanometers". 23 July 2020.
4. ^ International Roadmap for Devices and Systems: 2021 Update: More Moore, IEEE, 2021, p. 7, archived from the original on 7 August 2022, retrieved 7 August 2022
5. ^ "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". 10 September 2019. Archived from the original on 17 June 2020. Retrieved 20 April 2020.
6. ^ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Archived from the original on 2 December 2020. Retrieved 20 April 2021.
7. ^ "Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. Archived from the original on 15 July 2018. Retrieved 15 July 2018.
8. ^ "IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. 9 December 2002. Archived from the original on 31 May 2011. Retrieved 7 December 2017.
9. ^ Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). Extreme scaling with ultra-thin Si channel MOSFETs. Digest. International Electron Devices Meeting. pp. 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. S2CID 10151651.
10. ^ "NEC test-produces world's smallest transistor". Thefreelibrary.com. Archived from the original on 15 April 2017. Retrieved 7 December 2017.
11. ^ Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). Sub-10-nm planar-bulk-CMOS devices using lateral junction control. IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.
12. ^ "IMEC and Cadence Disclose 5nm Test Chip". Semiwiki.com. 4 July 2023. Retrieved 4 July 2023.
13. ^ "The Roadmap to 5nm: Convergence of Many Solutions Needed". Semi.org. Archived from the original on 26 November 2015. Retrieved 25 November 2015.
14. ^ Mark LaPedus (20 January 2016). "5nm Fab Challenges". Archived from the original on 27 January 2016. Retrieved 22 January 2016. Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
15. ^ Sebastian, Anthony (5 June 2017). "IBM unveils world's first 5nm chip". Ars Technica. Archived from the original on 5 June 2017. Retrieved 5 June 2017.
16. ^ Huiming, Bu (5 June 2017). "5 nanometer transistors inching their way into chips". IBM. Archived from the original on 9 June 2021. Retrieved 9 June 2021.
17. ^ "IBM Figures Out How to Make 5nm Chips". Uk.pcmag.com. 5 June 2017. Archived from the original on 3 December 2017. Retrieved 7 December 2017.
18. ^ a b Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". AnandTech. Archived from the original on 20 April 2019. Retrieved 31 May 2019.
19. ^ a b "TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology" (Press release). TSMC. 3 April 2019.
20. ^ "SALELE Double Patterning for 7nm and 5nm Nodes". LinkedIn. Archived from the original on 20 September 2021. Retrieved 25 March 2021.
21. ^ Jaehwan Kim; Jin Kim; Byungchul Shin; Sangah Lee; Jae-Hyun Kang; Joong-Won Jeon; Piyush Pathak; Jac Condella; Frank E. Gennari; Philippe Hurat; Ya-Chieh Lai (23 March 2020). Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes. Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280I. San Jose, California, United States. doi:10.1117/12.2551970.
22. ^ Solca, Bogdan (22 October 2019). "TSMC already sampling Apple's 5 nm A14 Bionic SoCs for 2020 iPhones". Notebookcheck. Archived from the original on 12 January 2020. Retrieved 12 January 2020.
23. ^ "TSMC Details 5 nm". 21 March 2020.
24. ^ "Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV".
25. ^ G. Yeap; et al. 5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing Applications. 2019 IEEE International Electron Devices Meeting (IEDM). doi:10.1109/IEDM19573.2019.8993577.
26. ^ Cutress, Dr Ian. "Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020". AnandTech. Archived from the original on 25 May 2020. Retrieved 19 December 2019.
27. ^ Hruska, Joel (25 August 2020). "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond". ExtremeTech. Archived from the original on 22 September 2020. Retrieved 12 September 2020.
28. ^ Patel, Dylan (27 October 2020). "Apple's A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC's Density Claims". SemiAnalysis. Archived from the original on 12 December 2020. Retrieved 29 October 2020.
29. ^ "TSMC Expands Advanced Technology Leadership with N4P Process". TSMC (Press release). 26 October 2021.
30. ^ "TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node". WikiChip. 26 October 2021. Archived from the original on 29 May 2022. Retrieved 28 May 2022.
31. ^ a b "TSMC Introduces N4X Process" (Press release). TSMC. 16 December 2021.
32. ^ a b "The Future Is Now (blog post)". TSMC. 16 December 2021. Archived from the original on 7 May 2022. Retrieved 25 May 2022.
33. ^ a b Shilov, Anton (17 December 2021). "TSMC Unveils N4X Node". AnandTech. Archived from the original on 25 May 2022. Retrieved 25 May 2022.
34. ^ a b Smith, Ryan. "Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance". AnandTech. Archived from the original on 13 June 2022. Retrieved 13 June 2022.
35. ^ Jones, Scotten (13 June 2022). "Intel 4 Deep Dive". SemiWiki.
36. ^ a b Schor, David (19 June 2022). "A Look At Intel 4 Process Technology". WikiChip Fuse.
37. ^ "AMD Launches Ryzen 7000 Series Desktop Processors with "Zen 4" Architecture: the Fastest Core in Gaming" (Press release). 29 August 2022. Retrieved 31 March 2023.
38. ^ Wickens, Katie (30 August 2022). "AMD's Lisa Su confirms chiplet-based RDNA 3 GPU architecture". PC Gamer. Retrieved 20 September 2022.
39. ^ "IRDS international roadmap for devices and systems 2017 edition" (PDF). Archived from the original (PDF) on 25 October 2018.
40. ^ a b c Jones, Scotten (29 April 2020), "Can TSMC Maintain Their Process Technology Lead", SemiWiki, archived from the original on 13 May 2022, retrieved 11 April 2022
41. ^ "Samsung Foundry Update 2019". SemiWiki. 6 August 2019. Archived from the original on 29 May 2022. Retrieved 14 May 2022.
42. ^ a b "Samsung 5 nm and 4 nm Update". WikiChip. 19 October 2019.
43. ^ a b "5 nm lithography process". WikiChip. Archived from the original on 6 November 2020. Retrieved 30 April 2017.
44. ^ a b c d "Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements". 5 July 2022.
45. ^ "NVIDIA Delivers Quantum Leap in Performance, Introduces New Era of Neural Rendering With GeForce RTX 40 Series". NVIDIA Newsroom. Retrieved 20 September 2022.
46. ^ "The TRUTH of TSMC 5nm".
47. ^ "N3E Replaces N3; Comes in Many Flavors". 4 September 2022.
48. ^ a b INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017, Section 4.5 Table MM-10 (p.12) entries : "SRAM bitcell area (um2)" ; "SRAM 111 bit cell area density - Mbits/mm2", archived from the original (PDF) on 25 October 2018, retrieved 24 October 2018
49. ^ a b c d "Did We Just Witness The Death Of SRAM?". 4 December 2022.
50. ^ J.C. Liu; et al. A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application. 2020 IEEE International Electron Devices Meeting (IEDM). doi:10.1109/IEDM13553.2020.9372009.
51. ^ "Samsung Foundry Vows to Surpass TSMC within Five Years".
52. ^ a b Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". AnandTech. Archived from the original on 3 November 2021. Retrieved 27 July 2021.
53. ^ Shilov, Anton (25 April 2024). "TSMC Preps Cheaper 4nm N4C Process for 2025, Aiming for 8.5% Cost Reduction". AnandTech.
54. ^ Formerly called Intel 7nm
55. ^ Bonshor, Gavin (20 October 2022). "Intel Core i9-13900K and i5-13600K Review: Raptor Lake Brings More Bite". AnandTech. Retrieved 28 September 2023.
56. ^ "TSMC N3, and Challenges Ahead". 27 May 2023.
57. ^ Gartenberg, Chaim (29 July 2021). "The summer Intel fell behind". The Verge. Archived from the original on 22 December 2021. Retrieved 22 December 2021.
58. ^ "Intel Unveils Meteor Lake Architecture: Intel 4 Heralds the Disaggregated Future of Mobile CPUs".
59. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Semiconductors.org. Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.
60. ^ "5 nm lithography process". WikiChip. Archived from the original on 6 November 2020. Retrieved 7 December 2017.
61. ^ "Samsung 3 nm GAAFET Node Delayed to 2024". 30 June 2021. Archived from the original on 17 December 2021. Retrieved 8 July 2021.
62. ^ Shilov, Anton. "Samsung: Deployment of 3nm GAE Node on Track for 2022". AnandTech. Archived from the original on 27 July 2021. Retrieved 27 July 2021.
63. ^ Shilov, Anton. "TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022". AnandTech. Archived from the original on 27 July 2021. Retrieved 27 July 2021.
64. ^ "15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". EE Times. 16 January 2017. Archived from the original on 28 June 2018. Retrieved 4 June 2018.

External links

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• 5 nm lithography process

Preceded by"7 nm" (FinFET)

MOSFET semiconductor device fabrication process

Succeeded by"3 nm" (FinFET/GAAFET)