CD40109B Data Sheet, Product Information And Support
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CMOS Quad Low-to-High Voltage Level Shifter (20V Rating)
Order now Data sheet- document-pdfAcrobat CD40109B TYPES datasheet (Rev. B)
CD40109B
ACTIVE Data sheet Order nowProduct details
Technology family CD4000 Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 3 High input voltage (max) (V) 18 Vout (min) (V) 577420 Vout (max) (V) 18 Data rate (max) (Mbps) 24 IOH (max) (mA) -6.8 IOL (max) (mA) -6.8 Supply current (max) (µA) 18 Features 22, 54.59, 79.56, 181.42 Input type Standard CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -55 to 125 Technology family CD4000 Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 3 High input voltage (max) (V) 18 Vout (min) (V) 577420 Vout (max) (V) 18 Data rate (max) (Mbps) 24 IOH (max) (mA) -6.8 IOL (max) (mA) -6.8 Supply current (max) (µA) 18 Features 22, 54.59, 79.56, 181.42 Input type Standard CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -55 to 125 PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4- Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD
- Up and down level-shifting capability
- Three-state outputs with separate enable controls
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range): = 1 V at VCC = 5 V, VDD = 10 V = 2 V at VCC = 10 V, VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
- Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations
Data sheet acquired from Harris Semiconductor
- Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD
- Up and down level-shifting capability
- Three-state outputs with separate enable controls
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range): = 1 V at VCC = 5 V, VDD = 10 V = 2 V at VCC = 10 V, VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
- Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations
Data sheet acquired from Harris Semiconductor
CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.
The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.
The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.
The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.
The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.
The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.
The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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TXH0137D-Q1 PREVIEW Automotive, fixed-direction, 7-bit 30-V voltage level translator with open-drain output Automotive qualified and higher voltage range with open drain outputTechnical documentation
star =Top documentation for this product selected by TI No results found. Please clear your search and try again. View all 12Type | Title | Date | |
---|---|---|---|
* | Data sheet | CD40109B TYPES datasheet (Rev. B) | 15 Jan 2003 |
Application note | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 02 Oct 2024 |
Application note | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 12 Jul 2024 |
Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 03 Jul 2024 |
Application brief | Leveraging TXH for High Voltage Level Shifting | PDF | HTML | 28 Jul 2023 |
Selection guide | Voltage Translation Buying Guide (Rev. A) | 15 Apr 2021 | |
Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | |
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | |
User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | |
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | |
User guide | Signal Switch Data Book (Rev. A) | 14 Nov 2003 | |
Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 03 Dec 2001 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
User guide: PDF | HTML Log in to order lock Log in to view inventory In stock Limit: Not available on TI.comPackage | Pins | CAD symbols, footprints & 3D models |
---|---|---|
PDIP (N) | 16 | Ultra Librarian |
SOP (NS) | 16 | Ultra Librarian |
TSSOP (PW) | 16 | Ultra Librarian |
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