Core M3-8100Y - Intel - WikiChip

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Core M3-8100Y - Intel < intel‎ | core m

Edit Values
M3-8100Y
General Info
Designer	Intel
Manufacturer	Intel
Model Number	M3-8100Y
Part Number	HE8067702739859
S-Spec	SRD23
Market	Mobile
Introduction	August 28, 2018 (announced)August 28, 2018 (launched)
Release Price	$281.00
Shop	Amazon
General Specs
Family	Core M3
Series	M3-8000
Locked	Yes
Frequency	1,100 MHz
Turbo Frequency	3,400 MHz (1 core),2,700 MHz (2 cores)
Bus type	OPI
Bus rate	4 GT/s
Clock multiplier	16
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Amber Lake
Chipset	Cannon Point
Core Name	Amber Lake Y
Core Family	6
Core Stepping	H0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	2
Threads	4
Max Memory	16 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	5 W
cTDP down	4.5 W
cTDP down frequency	600 MHz
cTDP up	8 W
cTDP up frequency	1,600 MHz
Packaging
Package	FCBGA-1515 (BGA)
Dimension	20 mm × 16.5 mm × 0.5 mm
Pitch	0.4 mm
Contacts	1515

Core M3-8100Y is a 64-bit dual-core low-end performance ultra-low power x86 mobile microprocessor introduced by Intel in 2018. This chip, which is based on the Amber Lake microarchitecture, is fabricated on Intel's 14 nm++ process. The M3-8100Y operates at 1.1 GHz with a TDP of 5 W and a turbo of 3.4 GHz. The processor supports up to 16 GiB of dual-channel LPDDR3-1866 memory and incorporates Intel's UHD Graphics 615 IGP operating at 300 MHz with a burst frequency of 900 MHz.

This processor has a configurable 4.5 W TDP-down and 8 W TDP-up.

Contents

• 1 Cache
• 2 Memory controller
• 3 Expansions
• 4 Graphics
• 5 Features

Cache[edit]

Main article: Amber Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB131,072 B 0.125 MiB L1I$ 64 KiB65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L1D$ 64 KiB65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 4-way set associative write-back L3$ 4 MiB4,096 KiB 4,194,304 B 0.00391 GiB     2x2 MiB 16-way set associative write-back

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3L-1600, LPDDR3-1866 Supports ECC No Max Mem 16 GiB Controllers 1 Channels 2 Max Bandwidth 27.81 GiB/s28,477.44 MiB/s 29.861 GB/s 29,860.76 MB/s 0.0272 TiB/s 0.0299 TB/s Bandwidth Single 13.9 GiB/sDouble 27.81 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 3.0 Max Lanes 10 Configs 1x4, 2x2, 1x2+2x1, 4x1

Graphics[edit]

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU UHD Graphics 615 Designer Intel Device ID 0x591E Execution Units 24 Max Displays 3 Max Memory 16 GiB16,384 MiB 16,777,216 KiB 17,179,869,184 B Frequency 300 MHz0.3 GHz 300,000 KHz Burst Frequency 900 MHz0.9 GHz 900,000 KHz Output DP, eDP, HDMI, DVI Max Resolution HDMI 4096x2304 @24 Hz DP 4096x2304 @60 Hz eDP 4096x2304 @60 Hz Standards DirectX 12 OpenGL 4.5 OpenCL 2.0 DP 1.2 eDP 1.4 HDMI 1.4a Additional Features Intel Quick Sync Video Intel InTru 3D Intel Clear Video Intel Clear Video HD

[Edit] Coffee Lake (Gen9.5) Hardware Accelerated Video Capabilities
Codec	Encode			Decode
	Profiles	Levels	Max Resolution	Profiles	Levels	Max Resolution
MPEG-2 (H.262)	Main	High	1080p (FHD)	Main	Main, High	1080p (FHD)
MPEG-4 AVC (H.264)	High, Main	5.1	2160p (4K)	Main, High, MVC, Stereo	5.1	2160p (4K)
JPEG/MJPEG	Baseline	-	16k x 16k	Baseline	Unified	16k x 16k
HEVC (H.265)	Main	5.1	2160p (4K)	Main	5.1	2160p (4K)
VC-1	✘			Advanced, Main, Simple	3, High, Simple	3840x3840
VP8	Unified	Unified	N/A	0	Unified	1080p
VP9	0	2160p (4K)	0, 2	Unified	2160p (4K)

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) MPX Memory Protection Extensions SGX Software Guard Extensions Secure Key Secure Key Technology SMEP OS Guard Technology Flex Memory Flex Memory Access ISRT Smart Response Technology MWT My WiFi Technology IPT Identity Protection Technology

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_m/m3-8100y&oldid=81886"Categories:

• all microprocessor models
• microprocessor models by intel
• microprocessor models by intel based on amber lake

Facts about "Core M3-8100Y - Intel"RDF feed

Has subobject"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core M3-8100Y - Intel#io +
base frequency	1,100 MHz (1.1 GHz, 1,100,000 kHz) +
bus rate	4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus type	OPI +
chipset	Cannon Point +
clock multiplier	16 +
core count	2 +
core family	6 +
core name	Amber Lake Y +
core stepping	H0 +
designer	Intel +
device id	0x591E +
family	Core M3 +
first announced	August 28, 2018 +
first launched	August 28, 2018 +
full page name	intel/core m/m3-8100y +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Identity Protection Technology +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel identity protection technology support	true +
has intel my wifi technology support	true +
has intel secure key technology	true +
has intel smart response technology support	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel turbo boost technology 2 0	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	UHD Graphics 615 +
integrated gpu base frequency	300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	24 +
integrated gpu max frequency	900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description	16-way set associative +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate	August 28, 2018 +
main image	+
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth	27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels	2 +
max pcie lanes	10 +
microarchitecture	Amber Lake +
model number	M3-8100Y +
name	M3-8100Y +
package	FCBGA-1515 +
part number	HE8067702739859 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 281.00 (€ 252.90, £ 227.61, ¥ 29,035.73) +
s-spec	SRD23 +
series	M3-8000 +
smp max ways	1 +
supported memory type	DDR3L-1600 + and LPDDR3-1866 +
tdp	5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
tdp down	4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) +
tdp down frequency	600 MHz (0.6 GHz, 600,000 kHz) +
tdp up	8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
tdp up frequency	1,600 MHz (1.6 GHz, 1,600,000 kHz) +
technology	CMOS +
thread count	4 +
turbo frequency (1 core)	3,400 MHz (3.4 GHz, 3,400,000 kHz) +
turbo frequency (2 cores)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

This page was last modified on 24 November 2024, at 10:57.

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