EE4321-VLSI CIRCUITS : HSPICE Simulation From Cadence' Interface

Spectre simulation using Cadence' Analog Design Environment

Follow the Steps :

1. For every cell that needs to be tested, we will generate a test schematic to keep things compartmentalised. For an inverter, create another cell called 'inverter_test' in your current library 'yourUNI'. Create a schematic view for this cell. For your convenience, the steps are mentioned again. Click on File --> New --> CellView in the CIW window (first window that opens with the program - the window named 'virtuoso'). Then enter Library Name as yourUNI, cellname as inverter_test and View Name as Schematic. This should pop-up an empty schematic creation window. In this window, you will generate a schematic as shown below:

To generate a schematic like this, you will need to go through the following steps. This assumes that you already have an inverter schematic instance and a corresponding symbol instance.

1 a. Place an instance of inverter by pressing 'i'. ( how to place an instance has already been discussed in " Cadence Schematic Editor Information" page). Make sure that you choose an inverter symbol from your library as your instance.

1 b. Place an instance for the dc voltage source. It is located in the 'analogLib' library and under the cell name 'vdc'. Click on 'symbol' and move your cursor to the schematic to place it down, far left, as in the figure above. Press 'q', then click on the component to enter the DC voltage value. Give it a value of 1.0V, or name the value as 'vdd' to make the voltage of the source a simulation design variable. Connect the voltage source to the inverter vdd/gnd supply pins and nets as shown.

1 c. Place an instance for the periodic square wave voltage source (vpulse), which you can find in the analogLib library and cell vpulse. Enter it's properties using 'q'. The vpulse source enables you to specify voltage source as a clock signal with 50% duty cycle. Enter the voltages as Voltage 1 as 0 V (gnd), and Voltage 2 as 1.0 V (or vdd, if you are making supply voltage a simulation design variable). Define the period as '1u', or 1us, corresponding to a frequency of 1 MHz.

1 d. Place an instance of a capacitor, which you can find under library analogLib and cell cap. A capacitor will simulate the effect of capacitive loading from the following stages. For illustration purposes, choose a value of 1pf for the capacitor. 1 e. Place the ground gnd symbol. It is under the name 'gnd' in the 'analogLib' library. the ground symbol defines your global ground for this circuit.

So we have created a test setup for the inverter, by giving it an input and having a capacitive load. Note that, in order to create labels for nets, press 'l' to create a label. This helps identifying nets to be plotted in simulations measuring input vin and output vout. Additionally, enabling display of component parameters in schematic view is also helpful. To do this, press 'q' after clicking on an component, then on the rightmost column of the CDF (Component Description Format) parameters section (the 'display' column), check the tickboxes of desired parameters to display.

2. Now we will simulate this inverter using Spectre in the Cadence Analog Design Environment. Re-open the inverter_test schematic window if you closed it. Choose Launch --> ADE L . You will see a window as shown below.

3.

1) On the bottom right corner of the ADE window, it should say 'Simulator: spectre'. If it does not, you should probably inform a TA. To change it manually so you can simulate, choose Setup --> Simulator/Directory/Host . A Choosing Simulator/Directory/Host window pops up. Choose 'spectre' as your simulator.

2) On the same screen, we need to specify where the simulation files will be stored. Your simulation files will easily exceed several hundred Megabytes, so you don't want this in your home directory which is uploaded to the server. You can use a directory called '/workdir' instead, which is in the current machine you're using. Next to 'Project directory' enter ' /workdir/yourUNI ' . Create the directory if you have to. Click on 'Host Mode' 'local', then press OK. * Note that the /workdir directory is not connected to the server, so if you move to another machine you will not be able to retrieve the simulation files. If you get space limit errors while simulating, try emptying the simulation files located in your machine's /workdir directory. * Also, if for some reason, ADE throws an error about permissions for /workdir, then something is not set up correctly, and you should let a TA know.

3a) We need to tell Cadence where to look to find our component models. These locations should be set by default, but if you wish to check, go to Setup --> Model Libraries.... A Model library setup window pops up. These lines should be under 'Global Model files':

3b) Update the 'Section' column entry corresponding to the blue boxed row from 'tt' to 'ff', as shown below:

4) Go to Setup --> Temperature and check that it is set at 27 degrees Celcius. Then, in the section defined as 'Design Variables', right click on it, then select 'Copy from Cellview'. If you have defined any design variables (i.e. by giving names to component CDF params instead of actual numbers), they will all be directly copied here. Left-click on the 'Value' column to numerically define these design variables. Here, I have defined vdd = 1.0 V and vin as 0 V

5) Now you have set up a simulation environment. In order to reuse the current settings in further simulations, go to Session --> Save state , give it a custom name (which is names 'state1' by default), and OK the window. This state will be tied particularly to your inverter_test schematic; to load it for use with other schematics, search the directory and look for it under this schematic.

4. Choose Analyses --> choose... You can perform either dc analysis which lets you sweep a dc voltage source or you can do transient analysis by choosing tran to observe the output as a function of time. ac and noise analysis is primarily used by analog designers to measure the frequency response and the noise performance of the circuit. In this tutorial we will focus on transient analysis. So, on the Choosing analyses window, click on tran and enter the 'stop time' as 5u. Click on 'moderate' for a reasonable measurement speed. Don't forget to choose Enabled at the bottom of the screen.

5. Go to Simulation menu in the Analog Design Environment window and click on Netlist and Run. (or you can press the green play button on the toolbar at the right end) This will start simulation. ( It is important to understand what Cadence does, when you hit a Run. It first creates a raw netlist having just the top-level instances and the include files. Next it generates a final netlist by bringing in all transistor level details. And finally, it runs the Spectre simulation. You can also go through these steps manually, by first clicking on Simulation --> Netlist -->Create and then press Run. Every step will show you an intermediate netlist output for your review. If you just press Run the first and only time, it will do all of this in one step, without showing you the intermediate netlist output) .

This will start the simulation process.

6. The CIW window should show " Reading Simulation Data ...... Successful", to ensure that simulation was a success. If not go to Simulation --> Output Log in your Analog Design Environment window to find out what the problem was. As an example, if you modified your tes schematic without saving changes (by pressing Shift+x), a simulation error will result. Your CIW and gray text windows will also contain information about warnings and errors. Now you can still continue with Cadence to view your results, which is mentioned below.

7. Go to Tools --> Calculator in the Analog Design Environment Window. A very useful tool "Calculator" will pop-up. It is a powerful graphical user interface used for viewing simulation results.

8. On the calculator, click on vt. This means you want to select a transient voltage on your schematic. When you click vt, go to your schematic window; the bottom border should say 'Select nets or terminals for VT expression' for VT expression. Now you click on one of the nets in your schematic window. You will see that the buffer screen of your calculator (the off-yellow box) shows the name of the net you just selected. Like in the above figure, I have "vout" selected. Now click plot on the calculator. (It is the icon with a calculator and a blue curve, circled in red) A new Waveform window will pop up with a Voltage vs. Time plot of the net you selected. To overlap the waveform of another net onto the same plot, go back to the calculator window, click vt, select different net, then click plot. Try showing waveforms of both in and out nets on the same plot. You can also add these expressions to the 'Outputs' section of the main ADE L window, by using the mechnical gear icon, circled in yellow. To add expressions to stack, click on the green arrow ico circled in blue. Pop & Insert icon will 'pop' these expressions back into the buffer window.

There is another way to simply view results. Go back to the Analog Design Environment window and go to Results --> Direct Plot --> Transient Signal. The schematic will come forward and it will let you select as many nets as you want until you press 'esc' on your keyboard. Click on the two nets, in this case, the wires going into and out of the inverter symbol, then press 'esc'. Now you should see a graph of both the input and output.

9. Finally, if you plot the in and out nets of your inverter_test schematic, you will see the input and output Voltage vs. Time plots of your inverter with a load of 1pF of capacitance. Try right-clicking your mouse and dragging it to form an area which you want to zoom in. You can always go back by pressing 'f', or clicking the 'zoom to fit' button. The result is shown in the window below. The red waveform shows the input to the inverter while the yellow one shows the output which as you can see is delayed due to the finite capacitive loading (see second picture for zoomed in view). To measure delay, press 'h' to set a horizontal cursor at Vm = Vdd/2, in this case 0.5 V. Press 'a' when mouse cursor is close to red waveform, and 'b' when mouse cursor is close to yellow wavform, to create a pair of vertical cursors with horizontal and vertical differences between them displayed. Move these cursors and their information display captions around as in the second plot below to measure the propogation delay t_p between the input signal and output signal.

Utilizing Various Tools in ADE

In the example above, we plotted the delay of an inverter as a response to a nearly-step input. However, the transient analysis is only one among many powerful tools provided by ADE. In this part of the tutorial we will briefly go over a few other useful analyses tools.

Fig N1

Figure N1 shows the ADE window. Notice the 1) Choose analyses button, 2) Edit Variables button.

1. First, by clicking the 'Choose analyses' button on the bar located on the right, you can again select the desired analysis type such as transient, ac, dc, ...

Fig N2

You can sweep a variable you want by either sweeping over a 'Design Variable' or a 'Component Parameter'. Let's first look at how to use the 'Component Parameter' option. For example, if you would like to make a dc voltage source sweep over a range: 1) select 'Component Parameter' as in the example 2) click on 'Select Component', and when the schematic window comes to the front, choose your voltage source 3) choose what you would like to sweep over: in this case, select 'dc'. 4) define the Sweep Range as needed, press OK.

2. Now let's find out how to sweep design variables. We already defined design variables earlier in the schematic cellview, and copied them over to ADE L 'Design Variables' section where we defined them with DC values. You can sweep one of your design variables at a time by choosing "Sweep Variable ->Design Variable" instead of "Sweep Variable -> Component Parameter" as we did previously in Figure N2.

Fig N3

3. As shown in Fig. N3, you can automate plotting selected outputs by taking advantage of the Outputs menu. Right-click the Outputs area and click Edit. Choose which variables (dc voltage, current, ...) at which nodes (nets) you would like to plot automatically after each simulation. To do this, you click on the 'From Design' button circled, then go to schematic to click on which nets you desire to plot. in the above, I have clicked on 'vin' and 'vout' nets, and they are correspondingly inside the 'Outputs' section. You can use the calculator to insert these into the Outputs section with an equation, as mentioned earlier. Now, when I run the DC simulation with design variable 'vin' being swept, I obtain the following VTC curve below (Fig. N4). Note that while the x and y axes are not explicitly labeled, its obvious the x-axis is 'vin' because that is the variable being swept in this DC simulation, while the y-axis is the 'vout' signal.

Fig N4

4. Finally, we will learn to use an extremely powerful tool called 'Parametric Analysis'. First, lets go back to inverter schematic cellview. Modify 'Multipliers' parameter of your NMOS to be named as 'nmos_multipliers', as shown below (Fig. N5). Do the same for the PMOS, naming its multipliers property as 'pmos multipliers'.

Fig N5

Once you have saved schematic changes, go back to your ADE window, and update design variables by right-clicking 'Copy from cellview'. Give DC values to NMOS and PMOS multipliers, lets say 10 for each (Fig. N6). Then go to Tools -> Parametric Analysis. A screen shown like in Fig. N7 will appear below:

Fig N6

Fig N7

Double-click 'Add Variable...' and choose the design variable you want to sweep. Define your sweep parameters (type, from, to, step number, etc.) and click the green play button (Netlist and Run). This tools allows you to execute whatever analysis you have in your ADE window, but multiple times over a third variable. For instance, if you want to see how x vs. y changes over a third variable z, the Parametric Analysis will be most useful. Note that you need to automate plotting by using the 'Outputs' section before you run Parametric Analysis, in order to visualize the effect of the third variable on the recurring simulations. For example, we can set a parametric analysis over 'nmos_multipliers' between 1 and 20, with step size 1 (Fig. N8). The resultant plot is below (Fig. N9).

Fig N8

Fig N9

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