Hybrid NVM Enabled Datacenter Design And Optimization Yanqi

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  • Corpus ID: 13406666
HNVM : Hybrid NVM Enabled Datacenter Design and Optimization Yanqi@inproceedings{Zhou2017HNVMH, title={HNVM : Hybrid NVM Enabled Datacenter Design and Optimization Yanqi}, author={Zhou and Ramnatthan Alagappan and Amirsaman Memaripour and Anirudh Badam and David Wentzlaff}, year={2017}, url={https://api.semanticscholar.org/CorpusID:13406666} }
  • ZhouRamnatthan Alagappan+2 authors D. Wentzlaff
  • Published 2017
  • Computer Science, Engineering
TLDRIt is proposed that storage intensive applications use more than one kind of NVM in configurable proportions to strike a balance between cost, performance and endurance.Expandmicrosoft.comSave to LibrarySaveCreate AlertAlertCiteShare14 CitationsBackground Citations7 Methods Citations2View All

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Topics

AI-GeneratedNon-volatile Memories (opens in a new tab)Phase Change Memory (opens in a new tab)Endurance (opens in a new tab)Battery-backed DRAM (opens in a new tab)Optimization (opens in a new tab)

14 Citations

Citation TypeHas PDFAuthorMore FiltersMore FiltersFiltersSort by RelevanceSort by Most Influenced PapersSort by Citation CountSort by Recency

Resource abstraction and data placement for distributed hybrid memory pool

    Ting-Hau ChenHaikun LiuXiaofei LiaoHai JinComputer Science, EngineeringFrontiers of Computer Science
  • 2021
TLDRAlly is proposed, a hotness-aware data placement scheme, which combines hot data migration, data replication and write merging together to improve application performance and reduce the cost of DRAM.Expand
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  • 2 Excerpts
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Design guidelines for high-performance SCM hierarchies

    Dmitrii UstiugovAlexandros Daglis+4 authors D. PnevmatikatosComputer Science, EngineeringMEMSYS
  • 2018
TLDRThis paper identifies the set of memory hierarchy design parameters that plays a key role in the performance and cost of a memory system combining an SCM technology and a 3D stacked DRAM cache, and introduces a methodology to drive provisioning for each of these design parameters under a target performance/cost goal.Expand
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Non-Volatile Memory Based Page Swapping for Building High-Performance Mobile Devices

    Duo LiuKan ZhongXiao ZhuYang LiLingbo LongZ. ShaoComputer Science, EngineeringIEEE Transactions on Computers
  • 2017
TLDRNVM-Swap is proposed by revisiting swapping for smartphones with fast, byte-addressable, non-volatile memory (NVM) technologies, and instead of using flash, builds the swap area with NVM, to allow high performance without sacrificing user experience.Expand
  • 25
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STASH: SecuriTy Architecture for Smart Hybrid Memories

    S. SwamiJoydeep RakshitK. MohanramComputer Science, Engineering2018 55th ACM/ESDA/IEEE Design Automation…
  • 2018
TLDRSTASH is the first comprehensive end-to-end SecuriTy Architecture for SHMs that integrates (i) counter mode encryption for data confidentiality, (ii) low overhead page-level Merkle Tree authentication for data integrity, (iii) recovery-compatible MT updates to withstand power/system failures, and (iv) page-migration-friendly security meta-data management.Expand
  • 14
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Software Wear Management for Persistent Memories

    V. GogteWilliam Wang+4 authors T. WenischComputer Science, EngineeringFAST
  • 2019
TLDRKevlar is presented, an OS-based wear-management technique for PM that requires no new hardware and achieves lifetime improvement of 18.4 × (avg.) over no wear management while incurring 1.2% performance overhead.Expand
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Hyperloop: group-based NIC-offloading to accelerate replicated transactions in multi-tenant storage systems

    Daehyeok KimAmirsaman Memaripour+7 authors S. SeshanComputer Science, EngineeringSIGCOMM
  • 2018
TLDRHyperLoop is presented, a new framework that removes CPU from the critical path of replicated transactions in storage systems by offloading them to commodity RDMA NICs, with non-volatile memory as the storage medium and demonstrates that popular storage applications can be easily optimized using these primitives.Expand
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TMC: Near-Optimal Resource Allocation for Tiered-Memory Systems

    Yuanjiang NiPankaj MehraE. L. MillerHeiner LitzComputer ScienceSoCC
  • 2023
TLDRThe novel configuration-selection algorithm incorporates a new heuristic, packing penalty, to ensure that recommended configurations will also achieve good resource efficiency, and reduces the search cost by up to 4× over the state-of-the-art, while improving resource utilization by 17% as compared to a naive policy that requests optimal tiered memory allocations in isolation.Expand
  • 8
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ESD: An ECC-assisted and Selective Deduplication for Encrypted Non-Volatile Main Memory

    Chunfeng DuSuzhen WuJiapeng WuBo MaoShengzhe WangComputer Science, Engineering2023 IEEE International Symposium on High…
  • 2023
TLDRESD utilizes the ECC information associated with each cache line evicted from the Last-Level Cache as the fingerprint to identify data similarity and avoids the costly hash calculating overhead on the non-duplicate cache lines.Expand
  • 9
  • 1 Excerpt
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FSDedup: Feature-Aware and Selective Deduplication for Improving Performance of Encrypted Non-Volatile Main Memory

    Chunfeng DuZihang Lin+6 authors Bo MaoComputer Science, EngineeringACM Trans. Storage
  • 2024
TLDRFSDedup can enhance the performance of the NVMM system further than the ESD and could leverage the prefetch cache to reduce the read overhead during similarity comparison and utilize the cache refresh mechanism to identify further and eliminate more redundant data.Expand
  • 1
  • PDF
  • 1 Excerpt
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OMT: A Run-time Adaptive Architectural Framework for Bonsai Merkle Tree-Based Secure Authentication with Embedded Heterogeneous Memory

    Rakin Muhammad ShadabYu ZouSanjay GandhamMingjie LinComputer Science, Engineering2023 IEEE International Symposium on Hardware…
  • 2023
TLDRA unified and hardware-friendly BMT framework called opportunistic Merkle tree (OMT), which is both modular and run-time adaptive by merging the logic for two different BMT update schemes while still allowing for parallel updates through separate update cores and eliminating the need for individual authentication subsystems for different memory modules in a heterogeneous memory platform.Expand
  • 6
  • 1 Excerpt
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31 References

Citation TypeHas PDFAuthorMore FiltersMore FiltersFiltersSort by RelevanceSort by Most Influenced PapersSort by Citation CountSort by Recency

Phase-Change Technology and the Future of Main Memory

    Benjamin C. LeePing Zhou+5 authors D. BurgerEngineering, Computer ScienceIEEE Micro
  • 2010
TLDRThis article discusses how to mitigate limitations through buffer sizing, row caching, write reduction, and wear leveling, to make PCM a viable dream alternative for scalable main memories.Expand
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Mojim: A Reliable and Highly-Available Non-Volatile Memory System

    Yiying ZhangJian YangAmirsaman MemaripourS. SwansonComputer Science, EngineeringASPLOS
  • 2015
TLDRMojim is proposed, a system that provides the reliability and availability that large-scale storage systems require, while preserving the performance of NVMM, by using a two-tier architecture in which the primary tier contains a mirrored pair of nodes and the secondary tier contains one or more secondary backup nodes with weakly consistent copies of data.Expand
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Page placement in hybrid memory systems

    Luiz E. RamosE. GorbatovR. BianchiniComputer Science, EngineeringICS '11
  • 2011
TLDRThis paper proposes a new hybrid design that features a hardware-driven page placement policy that is more robust and exhibits lower energy-delay2 than state-of-the-art hybrid systems.Expand
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Scalable high performance main memory system using phase-change memory technology

    Moinuddin K. QureshiVijayalakshmi SrinivasanJ. RiversEngineering, Materials ScienceISCA '09
  • 2009
TLDRThis paper analyzes a PCM-based hybrid main memory system using an architecture level model of PCM and proposes simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.Expand
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Exploiting Phase-Change Memory in Cooperative Caches

    Luiz E. RamosR. BianchiniComputer Science, Engineering2012 IEEE 24th International Symposium on…
  • 2012
TLDRThis paper exploits popularity information in placing objects across servers and memory technologies to improve the performance of cooperative memory caches in server clusters, and results show that DRAM-only and PCM-only memory systems do not perform well in all cases.Expand
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Log-structured memory for DRAM-based storage

    Stephen M. RumbleKejriwal A.J. OusterhoutComputer Science, EngineeringFAST
  • 2014
TLDRThe RAMCloud storage system implements a unified log-structured mechanism both for active information in memory and backup data on disk, which uses a two-level cleaning policy, which conserves disk bandwidth and improves performance up to 6× at high memory utilization.Expand
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A Practical Implementation of Clustered Fault Tolerant Write Acceleration in a Virtualized Environment

    Deepavali BhagwatMahesh PatilMichal OstrowskiM. VilayannurWoon JungC. KumarComputer Science, EngineeringFAST
  • 2015
TLDRFVP is introduced, a fault tolerant host-side flash write acceleration layer that seamlessly integrates with thevirtualized environment while preserving dynamic resource management and high availability, the holy tenets of a virtualized environment.Expand
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Mercury: Host-side flash caching for the data center

    Steve ByanJames LentiniAnshul MadanLuis PabonComputer Science, Engineering012 IEEE 28th Symposium on Mass Storage Systems…
  • 2012
TLDRMercury, a persistent, write-through host-side cache for flash memory designed as a hypervisor cache, simplifies integration and deployment into host environments and shows a 26% improvement in the bandwidth observed by the Jetstress benchmark and a 500% increase in the I/O rate of an enterprise workload.Expand
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Reliable Writeback for Client-side Flash Caches

    Dai QinAngela Demke BrownAshvin GoelComputer Science, EngineeringUSENIX ATC
  • 2014
TLDRThis work proposes two write-back based caching policies that provide strong reliability guarantees, under two different client failure models, and shows that these policies perform close to write- back caching, significantly outperforming write-through caching, for both read-heavy and write-heavy workloads.Expand
  • 46
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Flash Caching on the Storage Client

    David A. HollandE. AngelinoGideon WaldM. SeltzerComputer Science, EngineeringUSENIX ATC
  • 2013
TLDRIt is found that the chief benefit of the flash cache is its size, not its persistence, and for some workloads a large flash cache allows using miniscule amounts of RAM for file caching leaving more memory available for application use.Expand
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