Media-independent Interface - Wikipedia

The standard MII features a small set of registers:[2]: Section 22.2.4 "Management functions" 

• Basic Mode Configuration (#0)
• Status Word (#1)
• PHY Identifier (#2, #3)
• Auto-Negotiation Advertisement (#4)
• Auto-Negotiation Link Partner Base Page Ability (#5)
• Auto-Negotiation Expansion (#6)
• Auto-Negotiation Next Page Transmit (#7)
• Auto-Negotiation Link Partner Received Next Page (#8)
• MASTER-SLAVE Control Register (#9)
• MASTER-SLAVE Status Register (#10)
• PSE Control register (#11)
• PSE Status register (#12)
• MMD Access Control Register (#13)
• MMD Access Address Data Register (#14)

Register #15 is reserved; registers #16 through #31 are vendor-specific. The registers are used to configure the device and to query the current operating mode.[further explanation needed]

The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bit field with the following information:[2]: Section 22.2.4.2.2 "100BASE-X full duplex ability" 

Bit value	Meaning
0x8000	Capable of 100BASE-T4
0x6000	Capable of 100BASE-TX full/half duplex
0x1800	Capable of 10BASE-T full/half duplex
0x0600	Capable of 100BASE-T2 full/half duplex
0x0100	Extended status (Gigabit Ethernet) register exists
0x0080	Capable of unidirectional operation
0x0040	Management frame preamble suppression permitted
0x0020	Autonegotiation complete
0x0010	Remote fault
0x0008	Capable of Autonegotiation
0x0004	Link established
0x0002	Jabber detected
0x0001	Extended MII registers exist

Transmitter signals

edit

Signal name	Description	Direction
TX_CLK	Transmit clock	PHY to MAC
TXD0	Transmit data bit 0 (transmitted first)	MAC to PHY
TXD1	Transmit data bit 1	MAC to PHY
TXD2	Transmit data bit 2	MAC to PHY
TXD3	Transmit data bit 3	MAC to PHY
TX_EN	Transmit enable	MAC to PHY
TX_ER	Transmit error (optional)	MAC to PHY

The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s, 2.5 MHz for 10 Mbit/s). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle.

Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY.

More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an EEE-capable PHY to enter low power mode.

Receiver signals

edit

Signal name	Description	Direction
RX_CLK	Receive clock	PHY to MAC
RXD0	Receive data bit 0 (received first)	PHY to MAC
RXD1	Receive data bit 1	PHY to MAC
RXD2	Receive data bit 2	PHY to MAC
RXD3	Receive data bit 3	PHY to MAC
RX_DV	Receive data valid	PHY to MAC
RX_ER	Receive error	PHY to MAC
CRS	Carrier sense	PHY to MAC
COL	Collision detect	PHY to MAC

The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute.

The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost.

Similar to transmit, raising RX_ER outside a frame is used for special signaling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a false carrier indication.

The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists.

In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY.

Management signals

edit Main article: Management Data Input/Output

Signal name	Description	Direction
MDIO	Management data	Bidirectional
MDC	Management data clock	MAC to PHY

MDC and MDIO constitute a synchronous serial data interface similar to I²C. As with I²C, the interface is a multidrop bus so MDC and MDIO can be shared among multiple PHYs.

Limitations

edit

The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.