| Edit Values |
| Ryzen 3 3200G |
| General Info |
| Designer | AMD |
| Manufacturer | GlobalFoundries |
| Model Number | 3200G |
| Part Number | YD3200C5M4MFH, YD3200C5FHBOX |
| Market | Desktop |
| Introduction | June 12, 2019 (announced)July 7, 2019 (launched) |
| Release Price | $ 99 |
| Shop | Amazon |
| General Specs |
| Family | Ryzen 3 |
| Series | 3000 |
| Frequency | 3,600 MHz |
| Turbo Frequency | 4,000 MHz |
| Bus type | PCIe 3.0 |
| Clock multiplier | 36 |
| Microarchitecture |
| ISA | x86-64 (x86) |
| Microarchitecture | Zen+ |
| Core Name | Picasso |
| Process | 12 nm |
| Transistors | 4,940,000,000 |
| Technology | CMOS |
| Die | 209.78 mm² |
| Word Size | 64 bit |
| Cores | 4 |
| Threads | 4 |
| Max Memory | 64 GiB |
| Multiprocessing |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical |
| TDP | 65 W |
| cTDP down | 45 W |
| OP Temperature | 0° C – 95 °C |
| Packaging |
| Package | OPGA-1331 |
| Package Type | Organic Micro Pin Grid Array |
| Dimension | 40 mm × 40 mm |
| Pitch | 1 mm |
| Contacts | 1331 |
| Socket | Socket AM4 |
Ryzen 3 3200G is a 64-bit quad-core entry-level performance x86 desktop microprocessor introduced by AMD in mid 2019. This processor is based on AMD's Zen+ microarchitecture and is fabricated on a 12 nm process. The 3200G operates at a base frequency of 3.6 GHz with a TDP of 65 W and a Boost frequency of 4 GHz. This APU supports up to 64 GiB of dual-channel DDR4-2933 memory and incorporates Radeon Vega 8 Graphics operating at up to 1.25 GHz.
This model supports a configurable TDP-down of 45 W.
Contents
- 1 Cache
- 2 Memory controller
- 3 Expansions
- 4 Graphics
- 5 Features
- 6 Die
Cache[edit]
Main article: Zen+ § Cache [Edit/Modify Cache Info]
 | Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.Note: All units are in kibibytes and mebibytes. |
| L1$ | 384 KiB393,216 B 0.375 MiB | | L1I$ | 256 KiB262,144 B 0.25 MiB | 4x64 KiB | 4-way set associative | |
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| L1D$ | 128 KiB131,072 B 0.125 MiB | 4x32 KiB | 8-way set associative | write-back |
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| L2$ | 2 MiB2,048 KiB 2,097,152 B 0.00195 GiB | | | | 4x512 KiB | 8-way set associative | write-back |
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| L3$ | 4 MiB4,096 KiB 4,194,304 B 0.00391 GiB | |
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Memory controller[edit]
[Edit/Modify Memory Info]
 | Integrated Memory Controller |
| Max Type | DDR4-3200 |
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| Supports ECC | No |
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| Max Mem | 64 GiB |
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| Controllers | 2 |
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| Channels | 2 |
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| Max Bandwidth | 43.71 GiB/s44,759.04 MiB/s 46.933 GB/s 46,933.255 MB/s 0.0427 TiB/s 0.0469 TB/s |
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| Bandwidth | Single 21.86 GiB/sDouble 43.71 GiB/s |
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Expansions[edit]
The 3200G includes 20 PCIe lanes - 16 for a discrete graphics processor and 4 for storage (NVMe or 2 ports SATA Express).
[Edit/Modify Expansions Info]
 | Expansion Options |
| PCIe | | Revision | 3.0 |
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| Max Lanes | 20 |
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| Configs | 1x16+1x4 |
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| USB | | Revision | 3.0, 2.0 |
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| Ports | 4 |
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| Rate | 5 Gbit/s |
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Graphics[edit]
[Edit/Modify IGP Info]
 | Integrated Graphics Information |
| GPU | Radeon Vega 8 |
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| Designer | AMD |
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| Execution Units | 8 | Max Displays | 3 |
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| Unified Shaders | 512 |
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| Burst Frequency | 1,250 MHz1.25 GHz 1,250,000 KHz |
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| Output | DP, HDMI |
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| Standards | | DirectX | 12 |
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| OpenGL | 4.6 |
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| OpenCL | 2.2 |
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|
| [Edit] Zen with Radeon Vega Hardware Accelerated Video Capabilities |
| Codec | Encode | Decode |
| Max FPS | @1080p | @1440p | @2160p | @1080p 4:2:0 | @2160p 4:2:0 |
| MPEG-2 (H.262) | | 60 FPS | N/A |
| VC-1 |
| VP9 8bpc | 240 FPS | 60 FPS |
| VP9 10bpc |
| MPEG-4 AVC (H.264) 8bpc | 120 FPS | 60 FPS | 30 FPS |
| MPEG-4 AVC (H.264) 10bpc | |
| HEVC (H.265) 8bpc | 120 FPS | 60 FPS | 30 FPS |
| HEVC (H.265) 10bpc | |
| JPEG/MJPEG 8bpc |
Features[edit]
[Edit/Modify Supported Features]
 | Supported x86 Extensions & Processor Features |
| MMX | MMX Extension |
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| EMMX | Extended MMX Extension |
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| SSE | Streaming SIMD Extensions |
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| SSE2 | Streaming SIMD Extensions 2 |
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| SSE3 | Streaming SIMD Extensions 3 |
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| SSSE3 | Supplemental SSE3 |
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| SSE4.1 | Streaming SIMD Extensions 4.1 |
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| SSE4.2 | Streaming SIMD Extensions 4.2 |
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| SSE4a | Streaming SIMD Extensions 4a |
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| AVX | Advanced Vector Extensions |
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| AVX2 | Advanced Vector Extensions 2 |
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| ABM | Advanced Bit Manipulation |
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| BMI1 | Bit Manipulation Instruction Set 1 |
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| BMI2 | Bit Manipulation Instruction Set 2 |
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| FMA3 | 3-Operand Fused-Multiply-Add |
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| AES | AES Encryption Instructions |
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| RdRand | Hardware RNG |
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| SHA | SHA Extensions |
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| ADX | Multi-Precision Add-Carry |
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| CLMUL | Carry-less Multiplication Extension |
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| F16C | 16-bit Floating Point Conversion |
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| x86-16 | 16-bit x86 |
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| x86-32 | 32-bit x86 |
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| x86-64 | 64-bit x86 |
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| Real | Real Mode |
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| Protected | Protected Mode |
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| SMM | System Management Mode |
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| FPU | Integrated x87 FPU |
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| NX | No-eXecute |
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| SMT | Simultaneous Multithreading |
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| AMD-Vi | AMD-Vi (I/O MMU virtualization) |
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| AMD-V | AMD Virtualization |
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| SenseMI | SenseMI Technology |
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Die[edit]
Further information: Zen+ § Die - 12 nm process
- 4,940,000,000 transistors
- 209.78 mm² die size
