TN-41-13: DDR3 Point To Point Design Support - Micron - Yumpu

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TN-41-13: DDR3 Point to Point Design Support - Micron

TN-41-13: DDR3 Point to Point Design Support - Micron

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4Gb: x4, x8, x16 DDR3L-RS SDRAM - Micron 2GB, 4GB, 8GB (x64, DR) 240-Pin DDR3 UDIMM - Micron Micron ® PISMO ™ Module Data Sheet An Overview of SSD Write Caching (pdf) - Micron right - Micron Technical Note - Micron Numbers and Operations: Family Physician Problem: - Micron Putting SSDs to the Test - A Case Study - Micron DDR3 Advantages Presentation - Micron 400 MT/s NAND Interface Solutions - Micron Numbers and Operations: Full Charge Bookkeeper Problem: - Micron DDR SDRAM Point-to-Point Simulation Process Technical - Micron All You Need to Know About Mobile LPDRAM - Micron Micron FDI File System is Ideal for NOR-based Designs Micron High-Speed NAND Interface Product Flyer

Technical Note <strong>DDR3</strong> <strong>Point</strong>-<strong>to</strong>-<strong>Point</strong> <strong>Design</strong> <strong>Support</strong> Introduction <strong>TN</strong>-<strong>41</strong>-<strong>13</strong>: <strong>DDR3</strong> <strong>Point</strong> <strong>to</strong> <strong>Point</strong> <strong>Design</strong> <strong>Support</strong> Introduction <strong>Point</strong>-<strong>to</strong>-point design layouts have unique memory requirements, and selecting the right memory design methodology can be critical <strong>to</strong> a project’s success. While <strong>DDR3</strong> SDRAM was targeted for use on modules, it can easily be adapted for point-<strong>to</strong>-point applications. <strong>DDR3</strong> is an evolutionary transition from DDR2. <strong>DDR3</strong> point-<strong>to</strong>-point systems are similar <strong>to</strong> DDR2 point-<strong>to</strong>-point systems; both require similar design principles. But given that <strong>DDR3</strong> signaling is more critical, <strong>DDR3</strong> point-<strong>to</strong>-point systems require an emphasis on improving the data bus signaling. Before reviewing this technical note, a basic understanding of DDR2 point-<strong>to</strong>-point design methodologies and <strong>DDR3</strong> operation is recommended. <strong>Micron</strong>'s <strong>DDR3</strong> data sheet, along with the following technical notes, are available for reference on micron.com: • <strong>TN</strong>-00-20: Understanding the Value of Signal Integrity Testing • <strong>TN</strong>-<strong>41</strong>-02: <strong>DDR3</strong> ZQ Calibration • <strong>TN</strong>-<strong>41</strong>-04: Dynamic On-Die Termination • <strong>TN</strong>-46-02: Decoupling Capaci<strong>to</strong>r Calculation for a DDR Memory Channel • <strong>TN</strong>-46-06: Termination for <strong>Point</strong>-<strong>to</strong>-<strong>Point</strong> Systems • <strong>TN</strong>-46-11: DDR SDRAM <strong>Point</strong>-<strong>to</strong>-<strong>Point</strong> Simulation Process • <strong>TN</strong>-46-14: Hardware Tips for <strong>Point</strong>-<strong>to</strong>-<strong>Point</strong> System <strong>Design</strong>: Termination, Layout, and Routing • <strong>TN</strong>-47-19: DDR2 (<strong>Point</strong>-<strong>to</strong>-<strong>Point</strong>) Features and Functionality • <strong>TN</strong>-47-20: DDR2 (<strong>Point</strong>-<strong>to</strong>-Pont) Package Sizes and Layout Basics PDF: 09005aef84b67966 tn-<strong>41</strong>-<strong>13</strong>.pdf - Rev. A 07/12 EN 1 <strong>Micron</strong> Technology, Inc. reserves the right <strong>to</strong> change products or specifications without notice. © 2012 <strong>Micron</strong> Technology, Inc. All rights reserved. Products and specifications discussed herein are subject <strong>to</strong> change by <strong>Micron</strong> without notice.

  • Page 2 and 3: DDR2 to DDR3 SDRAM Comparison TN-41
  • Page 4 and 5: DDR3 Overview Memory Architecture T
  • Page 6 and 7: Reducing Values Calibration Control
  • Page 8 and 9: The figure below compares DDR2 and
  • Page 10 and 11: Return Path Trace Length Matching A
  • Page 12 and 13: TN-41-13: DDR3 Point to Point Desig
  • Page 14 and 15: Data Bus Topologies The DDR3 DQ bus
  • Page 16 and 17: Table 8: CMD/ADDR/CNTL Bus Terminat
  • Page 18 and 19: Figure 6: Tree Architecture with CM
  • Page 20 and 21: Figure 8: Tree vs. Fly-By Terminati
  • Page 22 and 23: Figure 11: Series R vs. ODT Termina
  • Page 24 and 25: Figure 12: DDR3 Addressing for Comp
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