Xeon Phi 7295 - Intel - WikiChip

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Xeon Phi 7295 - Intel < intel‎ | xeon phi

Edit Values
Xeon Phi 7295
General Info
Designer	Intel
Manufacturer	Intel
Model Number	7295
Part Number	HJ8068303823700
S-Spec	SR3VD
Market	Workstation, Server, Supercomputer
Introduction	December 18, 2017 (announced)December 18, 2017 (launched)
End-of-life	August 9, 2019 (last order)July 31, 2020 (last shipment)
Shop	Amazon
General Specs
Family	Xeon Phi
Series	x205
Locked	Yes
Frequency	1,500 MHz
Turbo Frequency	1,600 MHz (1 core)
Clock multiplier	15
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Knights Mill
Core Stepping	A0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	72
Threads	288
Max Memory	384 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	0.55 V-1.2 V
TDP	320 W
Tcase	5 °C – 77 °C
TDTS	5 °C – 94 °C
Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Xeon Phi 7295 is a 72-core x86 many-core microprocessor introduced by Intel in late 2017 specifically designed to accelerate artificial intelligence workloads. This processor, which is fabricated on their own 14 nm process based on the Knights Mill microarchitecture, operates at a frequency of 1.5 GHz with a TDP of 320 W and a turbo of 1.6 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Contents

• 1 Cache
• 2 Memory controller
• 3 Expansions
• 4 Features

Cache[edit]

Main article: Knights Mill § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.Note: All units are in kibibytes and mebibytes.

L1$ 4.5 MiB4,608 KiB 4,718,592 B L1I$ 2.25 MiB2,304 KiB 2,359,296 B 72x32 KiB 8-way set associative   L1D$ 2.25 MiB2,304 KiB 2,359,296 B 72x32 KiB 8-way set associative   L2$ 36 MiB36,864 KiB 37,748,736 B 0.0352 GiB     36x1 MiB 16-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2400 Supports ECC Yes Max Mem 384 GiB Controllers 2 Channels 6 Max Bandwidth 107.3 GiB/s109,875.2 MiB/s 115.212 GB/s 115,212.498 MB/s 0.105 TiB/s 0.115 TB/s Bandwidth Single 17.88 GiB/sDouble 35.76 GiB/sQuad 71.53 GiB/sHexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 36 Configuration: x16, x8, x4, x2, x1

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512ER AVX-512 Exponential and Reciprocal AVX512PF AVX-512 Prefetch AVX512_4FMAPS AVX-512 Fused Multiply-Accumulate Packed Single Precision AVX512_4VNNIW AVX-512 Vector Neural Network Instructions Word Variable Precision AVX512_VPOPCNTDQ AVX-512 Vector Population Count Doubleword and Quadword ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT)

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_phi/7295&oldid=90677"Categories:

• all microprocessor models
• microprocessor models by intel
• microprocessor models by intel based on knights mill
• microprocessor models require attention

Facts about "Xeon Phi 7295 - Intel"RDF feed

Has subobject"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Phi 7295 - Intel#pcie +
base frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) +
clock multiplier	15 +
core count	72 +
core stepping	A0 +
core voltage (max)	1.2 V (12 dV, 120 cV, 1,200 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
designer	Intel +
family	Xeon Phi +
first announced	December 18, 2017 +
first launched	December 18, 2017 +
full page name	intel/xeon phi/7295 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Intel VT-x +, Intel VT-d + and Extended Page Tables +
has intel turbo boost technology 2 0	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	4,608 KiB (4,718,592 B, 4.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	2,304 KiB (2,359,296 B, 2.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	2,304 KiB (2,359,296 B, 2.25 MiB) +
l2$ description	16-way set associative +
l2$ size	36 MiB (36,864 KiB, 37,748,736 B, 0.0352 GiB) +
last order	August 9, 2019 +
last shipment	July 31, 2020 +
ldate	December 18, 2017 +
main image	+
manufacturer	Intel +
market segment	Workstation +, Server + and Supercomputer +
max case temperature	350.15 K (77 °C, 170.6 °F, 630.27 °R) +
max cpu count	1 +
max dts temperature	94 °C +
max memory	393,216 MiB (402,653,184 KiB, 412,316,860,416 B, 384 GiB, 0.375 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
microarchitecture	Knights Mill +
min case temperature	278.15 K (5 °C, 41 °F, 500.67 °R) +
min dts temperature	5 °C +
model number	7295 +
name	Xeon Phi 7295 +
package	FCLGA-3647 +
part number	HJ8068303823700 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
s-spec	SR3VD +
series	x205 +
smp max ways	1 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2400 +
tdp	320 W (320,000 mW, 0.429 hp, 0.32 kW) +
technology	CMOS +
thread count	288 +
turbo frequency (1 core)	1,600 MHz (1.6 GHz, 1,600,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

This page was last modified on 10 May 2019, at 09:28.

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