VHDL Code For Seven-Segment Display On Basys 3 FPGA

Home » Code Vhdl Afficheur 7 Segment » VHDL Code For Seven-Segment Display On Basys 3 FPGA

Maybe your like

  • Home
  • FPGA Projects
  • Verilog Projects
  • VHDL Projects
  • FPGA Tutorial
  • Verilog vs VHDL
  • About
VHDL code for Seven-Segment Display on Basys 3 FPGA

Last time, I wrote a full FPGA tutorial on how to control the 4-digit 7-segment display on Basys 3 FPGA. A full Verilog code for displaying a counting 4-digit decimal number on the 7-segment display was also provided.

This VHDL project will present a full VHDL code for seven-segment display on Basys 3 FPGA. The seven-segment display on Basys 3 FPGA will be used to display a 4-digit hexadecimal number which is counting up every 1 second.

VHDL code for Seven-Segment Display on Basys 3 FPGA First of all, the truth table for BCD to 7-segment display decoder on Basys 3 FPGA is as follows: Truth table for BCD to 7-segment display on Basys 3 FPGA

VHDL code for BCD to 7-segment display decoder:

-- fpga4student: FPGA projects, Verilog projects, VHDL projects -- Example VHDL code for BCD to seven-segment display on Basys 3 FPGA process(LED_BCD) begin case LED_BCD is when "0000" => LED_out <= "0000001"; -- "0" when "0001" => LED_out <= "1001111"; -- "1" when "0010" => LED_out <= "0010010"; -- "2" when "0011" => LED_out <= "0000110"; -- "3" when "0100" => LED_out <= "1001100"; -- "4" when "0101" => LED_out <= "0100100"; -- "5" when "0110" => LED_out <= "0100000"; -- "6" when "0111" => LED_out <= "0001111"; -- "7" when "1000" => LED_out <= "0000000"; -- "8" when "1001" => LED_out <= "0000100"; -- "9" when "1010" => LED_out <= "0000010"; -- a when "1011" => LED_out <= "1100000"; -- b when "1100" => LED_out <= "0110001"; -- C when "1101" => LED_out <= "1000010"; -- d when "1110" => LED_out <= "0110000"; -- E when "1111" => LED_out <= "0111000"; -- F end case; end process;

Next, as I mentioned in the tutorial, a seven-segment display controller must be used to control the 4-digit seven-segment display on Basys 3 FPGA.

Below is the timing diagram for refreshing the 4-digit seven-segment display on Basys 3 FPGA: timing diagram of the 4-digit seven-segment display The refresh rate needed for the 4-digit seven-segment display is from 1ms to 16ms. Let's choose 10.5ms as the refresh period. Below is an example VHDL code for creating refresh rate and anode signals for the 4-digit seven-segment display on Basys 3 FPGA: -- 7-segment display controller -- generate refresh period of 10.5ms process(clock_100Mhz,reset) begin if(reset='1') then refresh_counter <= (others => '0'); elsif(rising_edge(clock_100Mhz)) then refresh_counter <= refresh_counter + 1; end if; end process; LED_activating_counter <= refresh_counter(19 downto 18); -- 4-to-1 MUX to generate anode activating signals for 4 LEDs process(LED_activating_counter) begin case LED_activating_counter is when "00" => Anode_Activate <= "0111"; -- activate LED1 and Deactivate LED2, LED3, LED4 LED_BCD <= displayed_number(15 downto 12); -- the first hex digit of the 16-bit number when "01" => Anode_Activate <= "1011"; -- activate LED2 and Deactivate LED1, LED3, LED4 LED_BCD <= displayed_number(11 downto 8); -- the second hex digit of the 16-bit number when "10" => Anode_Activate <= "1101"; -- activate LED3 and Deactivate LED2, LED1, LED4 LED_BCD <= displayed_number(7 downto 4); -- the third hex digit of the 16-bit number when "11" => Anode_Activate <= "1110"; -- activate LED4 and Deactivate LED2, LED3, LED1 LED_BCD <= displayed_number(3 downto 0); -- the fourth hex digit of the 16-bit number end case; end process;

Now, let's use it for displaying a counting hexadecimal number on the 4-digit seven-segment display on Basys 3 FPGA.

VHDL code for seven-segment display on Bays 3 FPGA:

-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects -- VHDL code for seven-segment display on Basys 3 FPGA library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; entity seven_segment_display_VHDL is Port ( clock_100Mhz : in STD_LOGIC;-- 100Mhz clock on Basys 3 FPGA board reset : in STD_LOGIC; -- reset Anode_Activate : out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals LED_out : out STD_LOGIC_VECTOR (6 downto 0));-- Cathode patterns of 7-segment display end seven_segment_display_VHDL; architecture Behavioral of seven_segment_display_VHDL is signal one_second_counter: STD_LOGIC_VECTOR (27 downto 0); -- counter for generating 1-second clock enable signal one_second_enable: std_logic; -- one second enable for counting numbers signal displayed_number: STD_LOGIC_VECTOR (15 downto 0); -- counting decimal number to be displayed on 4-digit 7-segment display signal LED_BCD: STD_LOGIC_VECTOR (3 downto 0); signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0); -- creating 10.5ms refresh period signal LED_activating_counter: std_logic_vector(1 downto 0); -- the other 2-bit for creating 4 LED-activating signals -- count 0 -> 1 -> 2 -> 3 -- activates LED1 LED2 LED3 LED4 -- and repeat begin -- VHDL code for BCD to 7-segment decoder -- Cathode patterns of the 7-segment LED display process(LED_BCD) begin case LED_BCD is when "0000" => LED_out <= "0000001"; -- "0" when "0001" => LED_out <= "1001111"; -- "1" when "0010" => LED_out <= "0010010"; -- "2" when "0011" => LED_out <= "0000110"; -- "3" when "0100" => LED_out <= "1001100"; -- "4" when "0101" => LED_out <= "0100100"; -- "5" when "0110" => LED_out <= "0100000"; -- "6" when "0111" => LED_out <= "0001111"; -- "7" when "1000" => LED_out <= "0000000"; -- "8" when "1001" => LED_out <= "0000100"; -- "9" when "1010" => LED_out <= "0000010"; -- a when "1011" => LED_out <= "1100000"; -- b when "1100" => LED_out <= "0110001"; -- C when "1101" => LED_out <= "1000010"; -- d when "1110" => LED_out <= "0110000"; -- E when "1111" => LED_out <= "0111000"; -- F end case; end process; -- 7-segment display controller -- generate refresh period of 10.5ms process(clock_100Mhz,reset) begin if(reset='1') then refresh_counter <= (others => '0'); elsif(rising_edge(clock_100Mhz)) then refresh_counter <= refresh_counter + 1; end if; end process; LED_activating_counter <= refresh_counter(19 downto 18); -- 4-to-1 MUX to generate anode activating signals for 4 LEDs process(LED_activating_counter) begin case LED_activating_counter is when "00" => Anode_Activate <= "0111"; -- activate LED1 and Deactivate LED2, LED3, LED4 LED_BCD <= displayed_number(15 downto 12); -- the first hex digit of the 16-bit number when "01" => Anode_Activate <= "1011"; -- activate LED2 and Deactivate LED1, LED3, LED4 LED_BCD <= displayed_number(11 downto 8); -- the second hex digit of the 16-bit number when "10" => Anode_Activate <= "1101"; -- activate LED3 and Deactivate LED2, LED1, LED4 LED_BCD <= displayed_number(7 downto 4); -- the third hex digit of the 16-bit number when "11" => Anode_Activate <= "1110"; -- activate LED4 and Deactivate LED2, LED3, LED1 LED_BCD <= displayed_number(3 downto 0); -- the fourth hex digit of the 16-bit number end case; end process; -- Counting the number to be displayed on 4-digit 7-segment Display -- on Basys 3 FPGA board process(clock_100Mhz, reset) begin if(reset='1') then one_second_counter <= (others => '0'); elsif(rising_edge(clock_100Mhz)) then if(one_second_counter>=x"5F5E0FF") then one_second_counter <= (others => '0'); else one_second_counter <= one_second_counter + "0000001"; end if; end if; end process; one_second_enable <= '1' when one_second_counter=x"5F5E0FF" else '0'; process(clock_100Mhz, reset) begin if(reset='1') then displayed_number <= (others => '0'); elsif(rising_edge(clock_100Mhz)) then if(one_second_enable='1') then displayed_number <= displayed_number + x"0001"; end if; end if; end process; end Behavioral;

Pin assignment constraint file for the 4-digit seven-segment display on Basys 3 FPGA:

# Clock signal set_property PACKAGE_PIN W5 [get_ports clock_100Mhz] set_property IOSTANDARD LVCMOS33 [get_ports clock_100Mhz] set_property PACKAGE_PIN R2 [get_ports reset] set_property IOSTANDARD LVCMOS33 [get_ports reset] #seven-segment LED display set_property PACKAGE_PIN W7 [get_ports {LED_out[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[6]}] set_property PACKAGE_PIN W6 [get_ports {LED_out[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[5]}] set_property PACKAGE_PIN U8 [get_ports {LED_out[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[4]}] set_property PACKAGE_PIN V8 [get_ports {LED_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[3]}] set_property PACKAGE_PIN U5 [get_ports {LED_out[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[2]}] set_property PACKAGE_PIN V5 [get_ports {LED_out[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[1]}] set_property PACKAGE_PIN U7 [get_ports {LED_out[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[0]}] set_property PACKAGE_PIN U2 [get_ports {Anode_Activate[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[0]}] set_property PACKAGE_PIN U4 [get_ports {Anode_Activate[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[1]}] set_property PACKAGE_PIN V4 [get_ports {Anode_Activate[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[2]}] set_property PACKAGE_PIN W4 [get_ports {Anode_Activate[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[3]}] Use the VHDL source file and constraint file, create a project in Vivado and run the VHDL code on Basys 3 FPGA. Below is the demo video for the seven-segment display on Basys 3 FPGA: Recommended VHDL projects:1. What is a FPGA? How VHDL works on FPGA2. VHDL code for FIFO memory3. VHDL code for FIR Filter4. VHDL code for 8-bit Microcontroller5. VHDL code for Matrix Multiplication6. VHDL code for Switch Tail Ring Counter7. VHDL code for digital alarm clock on FPGA8. VHDL code for 8-bit Comparator9. How to load a text file into FPGA using VHDL10. VHDL code for D Flip Flop11. VHDL code for Full Adder12. PWM Generator in VHDL with Variable Duty Cycle13. VHDL code for ALU14. VHDL code for counters with testbench15. VHDL code for 16-bit ALU16. Shifter Design in VHDL17. Nonlinear Lookup Table Implementation in VHDL18. Cryptographic Coprocessor Design in VHDL 19. Verilog vs VHDL: Explain by Examples 20. VHDL Code for Clock Divider on FPGA 21. Generate clock enable signal in VHDL 22. VHDL code for debouncing buttons on FPGA 23. VHDL code for Traffic light controller 24. VHDL code for a simple 2-bit comparator 25. VHDL code for a single-port RAM 26. VHDL code for Car Parking System using FSM 27. VHDL coding vs Software Programming 28. VHDL code for MIPS Processor 29. VHDL code for Moore FSM Sequence Detector 30. VHDL code for Seven-Segment Display on Basys 3 FPGA FPGA Verilog VHDL courses

11 comments:

  1. UnknownOctober 23, 2017 at 10:35 AM

    How to make a testbench for this project? any help would be appreciated.

    ReplyDeleteReplies
    1. UnknownOctober 24, 2017 at 6:26 AM

      Simply generate clock and reset in the testbench, then observe the simulation waveform. That's it.

      DeleteReplies
        Reply
    2. UnknownJanuary 15, 2020 at 5:59 AM

      Nope, doesnt work. Only thing you get to see is the clock and the reset. When you add other objects the values of them are "U" or "XXXXX"Please upload your testbench.

      DeleteReplies
        Reply
      3. Reply
  2. UnknownDecember 8, 2017 at 8:51 PM

    how to do counter down

    ReplyDeleteReplies
    1. UnknownDecember 8, 2017 at 9:46 PM

      simply change from displayed_number <= displayed_number + x"0001" to displayed_number <= displayed_number - x"0001";

      DeleteReplies
        Reply
      2. Reply
  3. Pablo SlayerDecember 18, 2017 at 6:10 PM

    :) <3

    ReplyDeleteReplies
      Reply
  4. UnknownMay 7, 2018 at 10:41 AM

    How to count until 10?

    ReplyDeleteReplies
      Reply
  5. James YangMay 27, 2018 at 1:00 AM

    Hello,I would like to know how to change the frequency and refresh rate?for like 1-second clock to 100Hz , 10.5ms to slightly faster.Thanks.

    ReplyDeleteReplies
      Reply
  6. AbcFebruary 28, 2020 at 2:05 PM

    How to write the same code using structure model?

    ReplyDeleteReplies
      Reply
  7. AbcMarch 1, 2020 at 3:37 PM

    Please tell me how to write the same code using structure modelling

    ReplyDeleteReplies
      Reply
  8. UnknownMay 15, 2020 at 3:50 PM

    does this work for DE0-Nano?

    ReplyDeleteReplies
      Reply
Add commentLoad more... Newer Post Older Post Home Subscribe to: Post Comments (Atom)

Trending FPGA Projects

  • Trending Verilog code and VHDL code on FPGA Image processing on FPGA using Verilog HDL This FPGA project is aimed to show in details how to process an image using Verilog from reading an input bitmap image (.bmp) in Verilog...
  • Trending Verilog code and VHDL code on FPGA Verilog code for D Flip Flop D Flip-Flop is a fundamental component in digital logic circuits. Verilog code for D Flip Flop is presented in this project. There are t...
  • Trending Verilog code and VHDL code on FPGA [FPGA Tutorial] Seven-Segment LED Display on Basys 3 FPGA This FPGA tutorial will guide you how to control the 4-digit seven-segment display on Basys 3 FPGA Board. A display controller will be ...
  • Trending Verilog code and VHDL code on FPGA Verilog Code for Ripple Carry Adder A Verilog code for a 4-bit Ripple-Carry Adder is provided in this project. The 4-bit ripple-carry adder is built using 4 1-bit full adde...
  • Trending Verilog code and VHDL code on FPGA Verilog code for Arithmetic Logic Unit (ALU) Last time , an Arithmetic Logic Unit ( ALU ) is designed and implemented in VHDL . Full VHDL code for the ALU was presented.  Today, f...
  • Trending Verilog code and VHDL code on FPGA Verilog code for Clock divider on FPGA Last time , I presented a VHDL code for a clock divider on FPGA. This Verilog project provides full Verilog code for the Clock Divider on...
  • Trending Verilog code and VHDL code on FPGA Verilog Code for 16-bit RISC Processor In this V erilog project , Verilog code for a 16-bit RISC processor is presented.  The RISC processor is designed based on its instructi...
  • Trending Verilog code and VHDL code on FPGA Verilog code for counter with testbench In this project, Verilog code for counters with testbench will be presented including up counter, down counter, up-down counter, and r...
  • Trending Verilog code and VHDL code on FPGA Verilog code for 16-bit single cycle MIPS processor In this project, a 16-bit single-cycle MIPS processor is implemented in Verilog HDL. MIPS is an RISC processor , which is widely used by ...
  • Trending Verilog code and VHDL code on FPGA Full Verilog code for Moore FSM Sequence Detector This Verilog project is to present a full Verilog code for Sequence Detector using Moore FSM . A Verilog Testbench for the Moore FSM sequ...
Support FPGA4Student

Join 18,000+ Followers

Facebook Twitter RSS Google+ Verilog VHDL Verification Tool

Popular FPGA projects

  • Popular Verilog code and VHDL code on FPGA Verilog code for D Flip Flop D Flip-Flop is a fundamental component in digital logic circuits. Verilog code for D Flip Flop is presented in this project. There are t...
  • Popular Verilog code and VHDL code on FPGA Verilog code for Arithmetic Logic Unit (ALU) Last time , an Arithmetic Logic Unit ( ALU ) is designed and implemented in VHDL . Full VHDL code for the ALU was presented.  Today, f...
  • Popular Verilog code and VHDL code on FPGA Image processing on FPGA using Verilog HDL This FPGA project is aimed to show in details how to process an image using Verilog from reading an input bitmap image (.bmp) in Verilog...
  • Popular Verilog code and VHDL code on FPGA [FPGA Tutorial] Seven-Segment LED Display on Basys 3 FPGA This FPGA tutorial will guide you how to control the 4-digit seven-segment display on Basys 3 FPGA Board. A display controller will be ...
  • Popular Verilog code and VHDL code on FPGA Verilog code for counter with testbench In this project, Verilog code for counters with testbench will be presented including up counter, down counter, up-down counter, and r...
  • Popular Verilog code and VHDL code on FPGA VHDL code for Seven-Segment Display on Basys 3 FPGA Last time , I wrote a full FPGA tutorial on how to control the 4-digit 7-segment display on Basys 3 FPGA. A full Verilog code for displayi...
  • Popular Verilog code and VHDL code on FPGA Verilog code for 16-bit single cycle MIPS processor In this project, a 16-bit single-cycle MIPS processor is implemented in Verilog HDL. MIPS is an RISC processor , which is widely used by ...
Verilog VHDL Verification Tool

Tag » Code Vhdl Afficheur 7 Segment