Chipset Based IBM PC/XT Compatible 8088 Board

1. It looks that AS6C1008 128 KiB SRAM chip doesn't have TTL compatible inputs (as opposed to AS6C4008 512 KiB SRAM). Using CMOS (74AHCT or possibly 74ACT) transceivers, buffers, and latches seems to help, but I'd like to test it further to make sure they work nicely with other ISA boards.
2. I am using BIOS copied from Intel Wildcard 88, which has some quirks. I'd like to port my own Xi 8088 BIOS to it.
3. NEC V20 doesn't want to work. I suspect the BIOS does something wrong

The 4008 lacks the second CE line (pin 30)

The 4008 lacks the second CE line (pin 30)

There is a spare inverter (U14a) that could be used to implement the second AS6C4008 by inverting the address line A19 onto pin 22 of the 2nd AS6C4008, This would negate the need for the second CE pin that the 1008 has (pin 30).

Sergey, Once this design is mature (production version) I would be interested in a blank PCB. regards David Fry

Any news lately on experiences with the prototypes? I might have the opportunity where I could get a board fabricated for my own use, and I was curious if the design is sufficiently mature, or if there are expected revisions. Scott

Did this resolve the V20 issues?

• Added 74F573 latch to fix the DMA issue
• Second SRAM changed to AS6C4008, 512 KiB part to fix the AS6C1008 TTL compatibility issue
• Second SRAM chip select is implemented using two 74F00 gates
• Added an option of using SPLD (ATF16V8B, GAL16V8) for SRAM address decode. This allows using available space in the second SRAM for UMBs
• CLK and OSC signals are now buffered through 74F244 instead of a pair of 74*04 gates
• Replaced 74ALS-series with 74F-series in the schematic and the PCB silkscreen. 74F are cheaper and faster (but 74ALS should work as well)
• PCB rerouted to accommodate the new parts, some components re-arranged to (hopefully) shorten trace lengths.
• PCB dimensions changed from 5"x4.3" to 6"x4" (152.4 mm x 101.6 mm). As the result the recommended ISA bracket changed to Keystone 9202.

This chipset will work with you Trident ISA SVGA Card?

Would it be a good idea to remove the GND connection from pin 3 of the speaker connector to prevent the possibility of an incorrect jumper across pins 3-4 causing a direct short of the 5V rail.

Now that you have a GAL in the design would it not be logical to generate the RAMCS2 signal inside the GAL, both RAMENA* and A19 are present on the GAL pins ?

Now that you have a GAL in the design would it not be logical to generate the RAMCS2 signal inside the GAL, both RAMENA* and A19 are present on the GAL pins ? This would eliminate 3 of the 4 gates in U14... The 4th gate is driving the speaker transistor Q1, you could in theory just use 2 of the spare pins on the GAL to perform the inverter function therby doing away with U14 altogether and giving youself a little more room in the top left corner of the PCB to play with. On the subject of the SPKR signal from 14 of the FE2010A, does pin 14 rest low or high when no sound is being produced ? If it rests low in its inactive state then no inverter is necessary, Q1 should only conduct when sound is being produced.

Would it be a good idea to remove the GND connection from pin 3 of the speaker connector to prevent the possibility of an incorrect jumper across pins 3-4 causing a direct short of the 5V rail.

When I built up my Xi 8088, I just removed that pin from the header, after reading what happened to a couple of the other builders on Vogons. An alternative would be to add provision for a PTC fuse or fusable link on the 5V line to that header.

PTC on the keyboard would be nice too. I once killed a keyboard fuse on a 386 motherboard by playing around with a custom keyboard implementation. Had there been no fuse, I would have probably killed the motherboard.

At first, I liked that the design is buildable without the GAL, as programmable logic often seems like mysterious black boxes to thwart my ability to understand and reverse engineer hardware that I find. That said, when I build one of these I'll probably include the GAL to get the UMB support anyway. I would think most people would choose to do this. Who doesn't want to make maximum use of that second 512K RAM chip?

Do you have enough space on the GAL to bank the extra space as EMM rather than or as well as UMB ? That way you could use all of it ?

While it is possible to use an external register file (e.g. a couple of 74LS670), that would further complicate the design.

If EMS is needed, I can suggest using this card.

3. Used SPLD to generate /RAMCS2 and the inverted speaker signal

U14 is still present on the PCB and in the schematic, it needs to be removed from the design to complete the change

Even better would be if A16 is normally under software control, granting easy software access to both lower and upper 64KB, so a software tool could easily flash both the main ROM and the "backup ROM" without the user moving any jumpers.

Any thoughts or suggestions about these modifications?

Even better would be if A16 is normally under software control, granting easy software access to both lower and upper 64KB...

Hmmm I wonder if one can be freed up somehow. Where can I find the datasheet for the FE2010A?